Not applicable.
Not applicable.
1. Field of the Invention
The present invention relates generally to sample and hold circuits and, more particularly, to a method and apparatus for extracting a time varying component of an analog signal while resetting the DC level of the signal to a new reference value.
2. Background Information
Sample and hold (S/H) stages are common in many analog circuits, for example in analog to digital converters and other applications where an analog signal needs to be sampled and held for some period of time. These circuits generally function by having a switch through which the input voltage which is to be sampled is supplied to the S/H circuit and a capacitor on which this sampled charge is stored. In the sample mode, the circuit output is derived from the input and the capacitor is charged. During the usually much longer hold mode, the output is based upon the changed placed on the capacitor by the input voltage during the brief sample mode.
An example of a prior art design is shown in FIG. 1a. In this particular design, the charge holding capacitor Chold 24 is part of a feedback loop to the same op-amp input that receives the input signal Vin, although a number of other placements can be found in other designs. This particular arrangement is an integrator-type S/H circuit. When switch S1 25 is closed and S2 26 is open, the circuit is in sample or track mode and charge accumulates on Chold 24. The equivalent circuit is shown in FIG. 1b. The DC gain is given by the ration of Rf 22 to Ri 23 and the overall transfer function is Vout=xe2x88x92(Rf/Ri)(1sRfChold)xe2x88x921Vin, where s is the Laplace transform parameter, so that it acts as an inverting low-pass circuit. The charge accumulated on Chold 24 is then proportional to Vout=xe2x88x92(Rf/Ri)(Vinxe2x88x92V+), where V+ is the voltage at the non-inverting terminal of op-amp 21.
The equivalent circuit during hold mode is shown in FIG. 1c. S1 25 is open and S2 26 is closed, and Vout is determined by the integrated charge stored on Chold 24 during the sample mode. S2 26 minimizes signal feedthrough when in hold mode and keeps the common node of the resistive network close to the voltage required when the circuit goes back to the sample mode.
One application of a sample and hold circuit is to extract a time varying component of an analog signal having a DC component of much greater amplitude than the time varying component. The circuit will need to pass and amplify the frequencies in the range of interest while at the same time largely removing any DC component. For example, if the circuit needs to extract a signal with a bandwidth of 10-1000 Hz embedded in an analog signal with a DC level several orders of magnitude larger this time varying portion, a S/H circuit as in FIG. 1 is inadequate: As a low pass filter, it will amplify the DC component (as well as any offset voltages passed on) more that the signal in the desired bandwidth; and if the resistors are chosen so that this bandwidth is amplified enough to be easily detectable, the DC level will have saturated the output thereby destroying any time varying component. Additionally, its low pass function makes it difficult to obtain a fast settling speed within acceptable values for the resistors and capacitor.
These problems can be reduced by giving the S/H circuit itself a high gain high pass filter function, combining it with additional stages high gain high pass sections, or both. The standard of doing this is to use a large capacitance either in place of, or in series with, the resistor Ri 23 in FIG. 1a. If an additional amplification stage with a standard, non-S/H high pass high gain filter function is added, it would be similar to FIG. 1 a with the integrating capacitor Chold 24 and the switches S1 25 and S2 26 removed, but a large capacitor would still be needed in the gain path. Although this sort of arrangement may give the desired response characteristics, it produces a number of new problems, largely related to the need for the large electrolytic capacitors in the gain path of the circuit. Additionally, when a gain of several orders of magnitude is needed for the wanted signal, any stray offset voltages are similarly magnified.
Having large capacitors causes several problems as such capacitors are not readily incorporated into an integrated circuit. Prior art solutions thus involve using discreet S/H circuits, resistors/capacitors, and operational amplifiers. This results in the reliability problems associated with discreet solutions, such as board leakage around the (usually FET) S/H and failure of the large electrolytic AC coupling capacitors in the signal path. Use of discreet components also limits the reduction both of the number of components and of the required board area. Additionally, these large off-chip capacitors have problems in radiation due to a susceptibility to induced electromagnetic fields.
The present invention provides a sample and hold circuit which uses an auto-zero feedback technique to cancel the DC level of the input signal and reference this signal to a new baseline. The circuit is based on an op-amp with two separate feedback loops. A first feedback loop is connected to the same op-amp input as the incoming signal and contains a capacitor to store charge from this signal during sample mode and set the output voltage during hold mode. The second feedback loop uses an auto-zero feedback technique and contains an integrator having a predetermined reference voltage, thereby allowing the DC level of the input signal to removed without the need for capacitors in the gain path of the circuit. This allows the sample and hold circuit to extract an embedded time varying signal from the input voltage. It can be configured for a high gain, high pass function, again without the need for large electrolytic capacitors in the gain path, removing the problems associated with such capacitors.
An exemplary embodiment is as a three stage circuit to extract an embedded signal lying in a frequency range, but having an amplitude much smaller than the DC component of the analog signal within which it is embedded. An initial low gain section acts as a buffer before the sample and hold section. Following the sample and hold section, the circuit employs a stage with a high gain high pass function also using auto-zero feedback. This again eliminates the large electrolytic capacitors usually placed in the gain path that can not be implemented as part of a single integrated circuit. Besides eliminating the need for off-chip capacitors in the gain path, by using auto-zero feedback all sample and hold errors are referenced to the output of the sample and hold stage and are not amplified by the total system in a multi-stage configuration as the offset voltages of the amplifiers are not amplified.
Additional objects, advantages, and features of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.